1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method therefor and, more particularly, to a semiconductor device having a highly dense mask programmable ROM portion of a dual poly-gate structure and a fabrication method therefor.
2. Description of the Prior Art
Exemplary mask ROM memory cells include a NAND ROM in which ROM data writing is achieved by selectively forming enhancement type cell transistors and depression type cell transistors to be connected in series, and a NOR ROM in which ROM data writing is achieved by selectively setting the threshold voltages of cell transistors connected in parallel at a level higher than a source voltage. In general, the NAND ROM is superior in integration density and inferior in operation speed, whereas the NOR ROM is superior in operation speed and inferior in integration density.
In view of this, a high density NOR ROM memory cell has been proposed which features both a high integration density and a high operation speed.
As shown in FIG. 17(a), the NOR ROM memory cell has a plurality of high concentration diffusion regions 55 provided in a parallel relation within a memory cell region having no device isolation film on a semiconductor substrate 51 and-serving as source/drain regions for cell transistors a, b and c and as bit line interconnections. The cell further has a plurality of gate electrodes (word lines) 53 formed on the semiconductor substrate 51 with intervention of a gate insulating film 52 and extending parallel to each other and perpendicularly to the high concentration diffusion regions 55. Device isolation regions 57 formed by implanting impurity ions of a conductivity different from that of the source/drain regions are provided in areas formed with neither the gate electrodes 53 nor the high concentration diffusion regions 55.
With this arrangement, the integration density in the memory cell region can be increased by reducing pitches of the high concentration diffusion regions 55 and the gate electrodes 53 to a level smaller than a conventional processibility limit, because the cell is free from steps which may otherwise be formed by the provision of a device isolation film. The device isolation is not achieved by the provision of the device isolation film but by self-aligned ion implantation after the formation of the gate electrodes 53. This also contributes to a higher integration density.
Further, a high density NOR ROM and NAND ROM have been proposed in which the integration density of memory cells is increased by employing a multi-gate structure which has a plurality of types of gate electrodes. For example, memory cells employing the multi-gate structure for a NAND ROM and for a highly dense NOR ROM are disclosed in Japanese Unexamined Patent Publications No. Sho 53(1978)-41188 and No. Sho 63(1988)-131568, respectively.
However, the high density NOR ROM memory cells employing the multi-gate structure have a difficulty in isolating the memory cells from each other.
In the case of conventional memory cells employing single-gate structure, the device isolation is achieved by implanting ions having the same conductivity as that of the substrate into areas where no gate electrode is formed after formation of the gate electrodes to increase the impurity concentration in the areas. In the case of memory cells employing dual-gate structure, however, the device isolation cannot properly be accomplished in the same manner as in the case of the memory cells of the single-gate structure, because ions cannot be implanted into an area where first gate electrodes and second gate electrodes are overlapped. As a result, a leak current between the memory cells is increased thereby to cause an operation failure.
To cope with this problem, Japanese Unexamined Patent Publications No. Hei 2(1990)-296339 and No. Hei 2(1990)-296366 propose methods of forming a device isolation region in an area where a first gate electrode and a second gate electrode are overlapped.
In accordance with Japanese Unexamined Patent Publication No. Hei 2(1990)-296339, source/drain regions 63 are formed in a semiconductor substrate 61 with the use of a resist mask 62 (FIG. 18(a)), and then first gate electrodes 65 each extending perpendicularly to the source/drain regions 63 are formed on the substrate 61 with a gate insulating film 64 interposed therebetween (FIG. 18(b)). Thereafter, ions 66 are implanted over the resulting substrate 61 with the use of the first gate electrodes 65 as a mask, and then side wall spacers 67 are formed on side walls of the first gate electrodes 65 (FIG. 18(c)). In turn, ion-implanted surface portions of the substrate 61 masked with the first gate electrodes 65 and the side wall spacers 67 are etched away (FIG. 18(d)), and then gate insulating films 68, second gate electrodes 69 and an interlayer insulating film 70 are formed on the resulting substrate (FIG. 18(e)).
In this method, however, the etching of the substrate 61 for the formation of the second gate electrodes 69 result in greater steps, thereby making it difficult to properly perform the subsequent processing. Further, surface portions of the substrate later serving as channel regions below the second gate electrodes 69 are subjected to the etching, resulting in deterioration of the gate insulating films 68 due to an etching damage and in variations in the impurity concentration in the channel regions due to variations in the etching degree. This increases variations in the transistor characteristics thereby to adversely influence the device operation.
In accordance with Japanese Unexamined Patent Publication No. Hei 2(1990)-296366, source/drain regions 73 are formed in a semiconductor substrate 71 with the use of a resist mask 72 (FIG. 19(a)). In turn, first gate electrodes 75 each extending perpendicularly to the source/drain regions 73 are formed on the substrate 71 with a gate insulating film 74 interposed therebetween, and then side wall spacers 76 and second gate insulating film 77 are formed (FIG. 19(b)). Thereafter, a second gate electrode material is deposited over the resulting substrate 71, and etched back to form second gate electrodes 78 between the first gate electrodes 75 (FIG. 19(c)). Subsequently, the side wall spacers 76 are removed by way of wet etching, and ions 79 are implanted into surface portions of the substrate 71 between the first gate electrodes 75 and the second gate electrodes 78 in a self-aligned manner for device isolation (FIG. 19(d)). Then, an interlayer insulating film 80 is formed on the resulting substrate (FIG. 19(e)).
In this method, however, it is difficult to control the wet etching of the side wall spacers 76 between the first gate electrodes 75 and the second gate electrodes 78. Accordingly, there is a possibility that the gate insulating films 74 an 77 are also etched, thereby presenting a problem associated with a gate breakdown voltage. Further, portions of the side wall spacers 76 remaining between the first gate electrodes 75 and the second gate electrodes 78 after the etching have thickness variations. This leads to variations in the concentration of the ions implanted into the substrate for the device isolation, thereby making the device isolation characteristics unstable.
As apparent from the foregoing, semiconductor devices and fabrication methods therefor which ensure both a higher integration density of memory cells and the reliable device isolation have not been realized yet.